1. Field of the Invention
The present invention relates to the field of semiconductor memory devices and, more particularly to a structure having improved static refresh properties in dynamic random access memory devices and a method of making it.
2. Description of the Related Art
Metal oxide semiconductor (MOS) structures are basic electronic devices used in many integrated circuits. One such structure is the metal oxide semiconductor field effect transistor (MOSFET), which is typically formed in a semiconductor substrate by providing a gate structure over the substrate to define a channel region, and by forming source and drain regions on opposing sides of the channel region.
To keep pace with the current trend toward maximizing the number of circuit devices contained in a single chip, integrated circuit designers continue to design integrated circuit devices with smaller and smaller feature sizes. For example, not too long ago it was not uncommon to have MOSFET devices (including CMOS devices) having channel lengths of 2 microns or more. The current state of the art for production MOSFET devices includes channel lengths of less than a xc2xc micron.
As the channel lengths of MOSFET devices have been reduced, MOSFETS have become more susceptible to certain problems. One common problem is increased junction leakage, a condition affecting the refresh characteristics of a dynamic random access memory (DRAM) memory cell. DRAM is a specific category of random access memory (RAM) containing an array of individual memory cells, where each cell includes a capacitor for holding a charge and a transistor for accessing the charge held in the capacitor. Due to junction leakage, the stored charge must be re-stored in the capacitor on a periodic basis through a process known as refresh. Increased junction leakage leads to a premature depletion of the capacitor""s stored charge, necessitating more frequent refresh cycles. Because resources are expended in refreshing the DRAM cells, the longer the period between refresh cycles, the better. The term xe2x80x9cpausexe2x80x9d is often used to represent the amount of time that a DRAM cell, or group of cells, can maintain their charge without undergoing a refresh operation. That is, how long can the DRAM control circuitry pause between refresh operations and still maintain the stored state of the DRAM memory cell. It is desirable to extend the pause period of, and improve the static refresh of, the DRAM.
A manufacturer may want to improve static refresh performance of the DRAM to provide customers with the capability to perform more memory operations (e.g., reads and writes) between refresh cycles. This reduces the overhead required to utilize the DRAM. Moreover, a manufacturer may want to improve static refresh performance to improve the operating specifications of the DRAM. For example, DRAMs typically have a low-power or standby specification requiring the DRAM to operate within a maximum current during a low-power mode. Since memory cells must be refreshed during the lower-power mode, reducing the frequency of the refresh operations will improve the DRAM""s operational performance for the low-power mode.
FIG. 1 illustrates a prior art MOSFET memory array device 5. The device 5 and its fabrication method are described in U.S. Pat. No. 5,534,449 (Dennison et al.), which is hereby incorporated by reference in its entirety. Briefly, the fabrication of the device 5 is initiated by forming a gate structure 10 on a substrate 8. The substrate 8 is typically a bulk silicon substrate, which may have a doped well therein in which transistors are formed. The gate structure 10 (referred to in the xe2x80x2449 patent as a gate line) typically comprises a gate oxide 12, a conductive polysilicon layer 14, an overlying WSix layer 16, an overlying novellus oxide layer 18 and a Si3N4 capping layer 20. The cross sectional width of this prior art gate structure 10 is 0.40 microns.
Once the gate structure 10 is formed, the device 5 is subjected to oxidizing conditions. This process step is often referred to as a xe2x80x9cre-oxxe2x80x9d step or a thermal re-ox step. Oxidized sidewalls 22, 24 are formed on the gate structure 10, and oxide regions 26, 28 are formed on the substrate, as a result of the re-ox step. Subsequent to the re-ox step, a blanket phosphorous implant step is performed to form diffusion regions 30, 32. This blanket phosphorous implant is performed at an energy level ranging from 30 Kev to 60 Kev with a dose ranging from 7xc3x971012 ions/cm2 to 1.5xc3x971013 ions/cm2 to provide an average dopant concentration for the diffusion regions 30, 32 ranging from 1xc3x971017 ions/cm3 to 1xc3x971019 ions/cm3. For the prior art device 5, this blanket phosphorous implant step is performed after the re-ox step to prevent the phosphorous from diffusing too far underneath the gate structure 10, which could cause transistor leakage problems.
The fabrication process of the device 5 typically includes the formation of oxide or nitride sidewall spacers 40, 42 on the sidewalls of the gate structure 10. Further processing may be performed as described in the ""449 patent. Although the MOSFET memory array device 5 is a vast improvement over earlier memory array devices, it can still benefit from improved static refresh performance. Thus, it is still desirable to improve as much as possible the static refresh performance of the memory device.
The present invention provides a memory array device having improved static refresh over prior art memory array devices.
The above and other features and advantages of the invention are achieved by a double blanket ion implant method for forming diffusion regions in memory array devices, such as a MOSFET access device. The method provides a semiconductor substrate with a gate structure formed on its surface. Next, a first pair of diffusion regions are formed in a region adjacent to the channel region by a first blanket ion implantation process. The first blanket ion implantation process has a first energy level and dose. The device is subjected to oxidizing conditions, which form oxidized sidewalls on the gate structure. A second blanket ion implantation process is conducted at the same location as the first ion implantation process adding additional dopant to the diffusion regions. The second blanket ion implantation process has a second energy level and dose. The resultant diffusion regions provide the device with improved static refresh performance over prior art devices. In addition, the first and second energy levels and doses are substantially lower than an energy level and dose used in a prior art single implantation process.